reading-testbench-variable-in-uvm-sequence
| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
| Why enable is not mentioned/passed as an argument? |
|
1 | 1044 | July 15, 2019 |
| ILLHIN illegal location for a hierarchical name(in a package) when accessing testbench top variable to uvm sequence |
|
0 | 4972 | March 31, 2015 |