Topics tagged macro

Topic	Replies	Views	Activity
Index resolution in a macro used in a generate block SystemVerilog SystemVerilog , generate , macro , index	3	1257	May 12, 2021
Registration macros UVM UVM , uvm_object_utils , uvm_component_utils , macro	1	934	April 7, 2021
Uvm_object_utils unexpected "SystemVerilog keyword 'typedef'" UVM SystemVerilog , UVM , macro	4	1527	March 15, 2021