Uvm_object_utils unexpected "SystemVerilog keyword 'typedef'"

I am new to UVM and i am trying to use the uvm_object_utils macro in a class for a sequence item.

Before using this macro included the uvm_macros.svh header file and imported the uvm_pkg like so:

import uvm_pkg::*;
`include “uvm_macros.svh”

I am using the uvm_object_utils macro in my code like so:

`uvm_object_utils(uvm_csv_packet_item)

when i go to compile this file with the following commands (i am trying with and without the +incdir+$UVM_HOME)

vlog +incdir+$UVM_HOME/src uvm_csv_seq_item.sv
or
vlog uvm_csv_seq_item.sv

i get the message:

** Error: (vlog-13069) ** while parsing macro expansion: ‘uvm_object_utils’ starting at uvm_csv_seq_item.sv(17)

** at uvm_csv_seq_item.sv(17): near “typedef”: syntax error, unexpected “SystemVerilog keyword ‘typedef’”, expecting implements or ‘;’.

i am trying to interpret this message…

It seems to be telling me that the macro uvm_object_utils contains a "unexpected “SystemVerilog keyword ‘typedef’…”

Why is my compiler confused?

In reply to mreister:

Many SystemVerilog syntax errors are because of problems before the reported error line number. It would help if you showed the code from the class declaration header up to the reported error.

In reply to dave_59:

ifndef NAME_OF_SEQ_ITEM_SV define NAME_OF_SEQ_ITEM_SV

import uvm_pkg::*;
`include “uvm_macros.svh”

class uvm_csv_packet_item extends uvm_sequence_item

`uvm_object_utils(uvm_csv_packet_item)

Above is the code up to the line that is reporting the error. I have removed the comments for simplicity.

The line with the uvm_object_utils macro is what is giving me this error.

In reply to mreister:

The class declaration is missing a semicolon ‘;’

In reply to dave_59:

Oh. Thanks! I am new at this.