UVM-SystemVerilog
Topic | Replies | Views | Activity | |
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My test cannot start 2 sequence at the same time |
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4 | 876 | June 30, 2022 |
The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it |
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38 | 14613 | November 30, 2021 |
Can't understand how covergroup sample works |
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24 | 5553 | June 15, 2019 |
Peeking into internal signal |
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2 | 2080 | August 10, 2016 |