Peeking into internal signal

UVM
,
1

Hi,
I am writing a UVM verification environment for a VHDL DUT.
The DUT has internal signal whose type is array of user defined VHDL record, e.g.:
type my_record is record
a : std_logic;
b : std_logic;
end record;
type my_array_of_records is array(0 to 3) of my_record;

I want to peek into this internal signal.
so I wrote in my interface definition:
my_record internal_VHDL_record[0 to 3];

and in the top level module I wrote:
generate
genvar ch;
for (ch = 0;ch < 4;ch++)
assign u_interface.internal_VHDL_record[ch] = top.module_a_inst.internal_signal[ch];
endgenerate

where top.module_a_inst.internal_signal is the full path to the internal array of records.
What I see is that the u_interface.internal_VHDL_record gets initial values(i.e. zero values and not “U”), but when the internal VHDL signals changes, the interface signal does not.
Can you suggest why?
Thanks

2

In reply to shaygueta:
I guess this is a tool specific issue and hence contact your vendor. If you want a portable solution you can use VHDL extern signals and try, or use a probe_pkg that we had release few years back that internally uses signal-spy like API.

Srini
www.go2uvm.org

3

In reply to shaygueta:

VHDL was not transparent to the einvironment until VHDL-2008 came to live, i.e. you cannot look into internals of a VHDL design by definition. VHDL broke this rule now VHDL is transparent. To enable this feature you have to compile your VHDL code for VHDL-2008, i.e. corresponding switch.