The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it

Error-[NOA] Null object access
The object at dereference depth 1 is being used before it was
Please make sure that the object is allocated before using it.

#0 in

#1 in \calc_driver::run_phase at

How can I solve it ?

`include ""
class calc_driver extends uvm_driver #(calc_trans);

  virtual calc_if dut_ifc1;

  function new(string name, uvm_component parent);,parent);
  endfunction: new

  function void build_phase(uvm_phase phase);
       if(!uvm_config_db#(virtual calc_if)::get(this,"","dut_vif", dut_ifc1))
       `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".dut_ifc"}); 
  endfunction: build_phase

  task run_phase(uvm_phase phase);
      calc_trans req;
     $display("driver get_next_item");      
   // @(posedge dut_ifc1.clk);
     // @( negedge dut_ifc1.clk)
     $display("driver get_next_item after");      
       dut_ifc1.a <= req.a;
       dut_ifc1.b <= req.b;
       dut_ifc1.opcode <= req.opcode;
       // @( posedge dut_ifc1.clk);
  endtask: run_phase
 endclass: calc_driver

In reply to alexd555:

Could you please show what is line 25 of file


In reply to alexd555:

Then there no seq_item has been generated by the sequencer.
Could you please show the body_task of the corresponding sequence you are running on the sequencer?

class calc_sequence extends uvm_sequence#(calc_trans);

  function new(string name = "calc_sequence");;
	endfunction: new

	task body();
		calc_trans req;
		repeat(2) begin
		req = calc_trans::type_id::create("req");
	endtask: body
endclass: calc_sequence
typedef uvm_sequencer#(calc_trans) calc_sequencer;

In reply to alexd555:

This looks OK. Does the connection between seq_item_export (sequencer) and the seq_item_port (driver) exist?

How can I check it ?
Where do I need to do it ?

In reply to alexd555:

This has to be done in the connect_phase of the agent.

`include ""
`include ""
`include ""
`include ""
`include ""
class calc_agent extends uvm_agent;
  uvm_analysis_port #(calc_trans)  aport;

 calc_sequencer calc_sequencer_h;
 calc_driver calc_driver_h;
 calc_monitor calc_monitor_h;
  function new(string name="calc_agent", uvm_component parent);, parent);
	endfunction: new
  function void build_phase(uvm_phase phase);
   aport = new ("aport", this);
    calc_sequencer_h = calc_sequencer::type_id::create("calc_sequencer", this);
    calc_driver_h = calc_driver::type_id::create("calc_driver", this);
    calc_monitor_h = calc_monitor::type_id::create("calc_monitor", this);
  endfunction: build_phase

  function void connect_phase(uvm_phase phase);
  endfunction: connect_phase
endclass: calc_agent

You are right. I forgot it:

But I have another problem. The test runs forever. I replace “forever” to repeat but it doesn’t help.

I get:
objections raised, skipping phase

In reply to alexd555:

In the connect_phase the connection between the driver and the sequencer is missing:


What about
Phase ‘uvm.uvm_sched.post_shutdown’ (id=324) No objections raised, skipping phase

In reply to alexd555:

Is this your error message you get or what is it?

Another problem,
dump is not created

module calc_tb_top;
import uvm_pkg::*;

//clock and reset signal declaration
logic clk;
logic reset;

//creatinng instance of interface, inorder to connect DUT and testcase
calc_if dut_ifc1(clk, reset);

//enabling the wave dump

  initial begin
  forever begin
  clk = ~clk;

//DUT instance, interface signals are connected to the DUT ports
calculator DUT (

 initial begin
     uvm_config_db#(virtual calc_if)::set(null,"*","dut_vif", dut_ifc1);


initial begin


In reply to alexd555:

Did you close the simulator? It might flash the buffer only after closing the simulation.
BTW, why do you use the $dumpvars/$dumpfile? In the simulator you are able to display all signals/variables in the wave window.

I closed.

The clock is not generated.

I use with synopsis vcs

In reply to alexd555:

Then you know where it comes from …
In such a case check always the progress in time. If it stucks at runtime 0 you’ll not see any waveform.

it doesn’t stuck.

Do you have any idea ?

$finish at simulation time 0
V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.830 seconds; Data structure size: 0.5Mb
Thu Jun 13 13:21:50 2019
CPU time: 10.461 seconds to compile + .536 seconds to elab + .752 seconds to link + .888 seconds in simulation

Do you have idea how I can solve it ?