Another problem,
dump is not created
module calc_tb_top;
import uvm_pkg::*;
//clock and reset signal declaration
logic clk;
logic reset;
//creatinng instance of interface, inorder to connect DUT and testcase
calc_if dut_ifc1(clk, reset);
//enabling the wave dump
initial begin
forever begin
#5ns;
clk = ~clk;
end
end
//DUT instance, interface signals are connected to the DUT ports
calculator DUT (
.clk(dut_ifc1.clk),
.rstn(dut_ifc1.rstn),
.a(dut_ifc1.a),
.b(dut_ifc1.b),
.opcode(dut_ifc1.opcode),
.result(dut_ifc1.res),
.error(dut_ifc1.error)
);
initial begin
uvm_config_db#(virtual calc_if)::set(null,"*","dut_vif", dut_ifc1);
$dumpfile("b.vcd");
$dumpvars;
end
initial begin
run_test(“calc_test”);
end
endmodule