In reply to alexd555:
Could you please show what is line 25 of file calc_driver.sv.
seq_item_port.get_next_item(req);
In reply to alexd555:
Then there no seq_item has been generated by the sequencer.
Could you please show the body_task of the corresponding sequence you are running on the sequencer?
calc_sequence.sv
class calc_sequence extends uvm_sequence#(calc_trans);
`uvm_object_utils(calc_sequence)
function new(string name = "calc_sequence");
super.new(name);
endfunction: new
task body();
calc_trans req;
repeat(2) begin
req = calc_trans::type_id::create("req");
start_item(req);
assert(req.randomize());
finish_item(req);
end
endtask: body
endclass: calc_sequence
calc_sequencer.sv
typedef uvm_sequencer#(calc_trans) calc_sequencer;
In reply to alexd555:
This looks OK. Does the connection between seq_item_export (sequencer) and the seq_item_port (driver) exist?
How can I check it ?
Where do I need to do it ?
calc_agent.sv
`include "calc_trans.sv"
`include "calc_sequencer.sv"
`include "calc_driver.sv"
`include "calc_monitor.sv"
`include "calc_scoreboard.sv"
class calc_agent extends uvm_agent;
`uvm_component_utils(calc_agent)
uvm_analysis_port #(calc_trans) aport;
calc_sequencer calc_sequencer_h;
calc_driver calc_driver_h;
calc_monitor calc_monitor_h;
function new(string name="calc_agent", uvm_component parent);
super.new(name, parent);
endfunction: new
function void build_phase(uvm_phase phase);
aport = new ("aport", this);
calc_sequencer_h = calc_sequencer::type_id::create("calc_sequencer", this);
calc_driver_h = calc_driver::type_id::create("calc_driver", this);
calc_monitor_h = calc_monitor::type_id::create("calc_monitor", this);
endfunction: build_phase
function void connect_phase(uvm_phase phase);
calc_monitor_h.aport.connect(this.aport);
endfunction: connect_phase
endclass: calc_agent
You are right. I forgot it:
calc_driver_h.seq_item_port.connect(calc_sequencer_h.seq_item_export);
But I have another problem. The test runs forever. I replace “forever” to repeat but it doesn’t help.
I get:
objections raised, skipping phase
In reply to alexd555:
In the connect_phase the connection between the driver and the sequencer is missing:
calc_driver_h.seq_item_port.connect(calc_sequencer_h.seq_item_export);
What about
Phase ‘uvm.uvm_sched.post_shutdown’ (id=324) No objections raised, skipping phase
?
Another problem,
dump is not created
module calc_tb_top;
import uvm_pkg::*;
//clock and reset signal declaration
logic clk;
logic reset;
//creatinng instance of interface, inorder to connect DUT and testcase
calc_if dut_ifc1(clk, reset);
//enabling the wave dump
initial begin
forever begin
#5ns;
clk = ~clk;
end
end
//DUT instance, interface signals are connected to the DUT ports
calculator DUT (
.clk(dut_ifc1.clk),
.rstn(dut_ifc1.rstn),
.a(dut_ifc1.a),
.b(dut_ifc1.b),
.opcode(dut_ifc1.opcode),
.result(dut_ifc1.res),
.error(dut_ifc1.error)
);
initial begin
uvm_config_db#(virtual calc_if)::set(null,"*","dut_vif", dut_ifc1);
$dumpfile("b.vcd");
$dumpvars;
end
initial begin
run_test(“calc_test”);
end
endmodule
In reply to alexd555:
Did you close the simulator? It might flash the buffer only after closing the simulation.
BTW, why do you use the $dumpvars/$dumpfile? In the simulator you are able to display all signals/variables in the wave window.
I closed.
The clock is not generated.
I use with synopsis vcs
In reply to alexd555:
Then you know where it comes from …
In such a case check always the progress in time. If it stucks at runtime 0 you’ll not see any waveform.
it doesn’t stuck.
Do you have any idea ?
$finish at simulation time 0
V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.830 seconds; Data structure size: 0.5Mb
Thu Jun 13 13:21:50 2019
CPU time: 10.461 seconds to compile + .536 seconds to elab + .752 seconds to link + .888 seconds in simulation
Do you have idea how I can solve it ?
In reply to alexd555:
Looks like your clock is not working or you did not implement an objection mechanism.