In reply to alexd555:
Looks like your clock is not working or you did not implement an objection mechanism.
How can I check ?
In reply to alexd555:
Look into your toplevel module if there is a clock generator. Afterwards look to your driver. It might hang at time 0.
If possible post the beginning of your run_phase of the driver around get_next_item.
Objections have to be implemented. They can be in different places. Look to your test, driver and sequences. These are the most common constructs objections can be implemented.
I posted my toplevel model. You can there is a clock(clk).
calc_driver.sv
include "calc_sequence.sv" class calc_driver extends uvm_driver #(calc_trans); uvm_component_utils(calc_driver)
virtual calc_if dut_ifc1;
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction: new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(virtual calc_if)::get(this,“”,“dut_vif”, dut_ifc1))
`uvm_fatal(“NOVIF”,{“virtual interface must be set for: “,get_full_name(),”.dut_ifc”});
$display(“driver”);
endfunction: build_phase
task run_phase(uvm_phase phase);
repeat(300)
begin
calc_trans tx;
seq_item_port.get_next_item(tx);
dut_ifc1.a <= tx.a;
dut_ifc1.b <= tx.b;
dut_ifc1.opcode <= tx.opcode;
seq_item_port.item_done();
end
endtask: run_phase
endclass: calc_driver
calc_sequence.sv
class calc_sequence extends uvm_sequence#(calc_trans);
`uvm_object_utils(calc_sequence)
function new(string name = “calc_sequence”);
super.new(name);
endfunction: new
task body();
calc_trans req;
$display("calc_seq");
repeat(300) begin
req = calc_trans::type_id::create("req");
start_item(req);
assert(req.randomize());
finish_item(req);
$display("a = ", req.a);
$display("b = ", req.b);
$display("opcode = ", req.opcode);
end
endtask: body
endclass: calc_sequence
calc_test.sv
class calc_test extends uvm_test;
`uvm_component_utils(calc_test)
calc_env env;
calc_sequence calc_seq;
function new(string name = “calc_test”,uvm_component parent=null);
super.new(name,parent);
endfunction : new
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
env = calc_env::type_id::create(“env”, this);
calc_seq = calc_sequence::type_id::create(“calc_seq”, this);
endfunction : build_phase
task run_phase(uvm_phase phase);
phase.raise_objection(this);
calc_seq.start(env.calc_agent_h.calc_sequencer_h);
phase.drop_objection(this);
endtask : run_phase
endclass : calc_test
In reply to alexd555:
The run_phase of your driver is not a clocked process, i.e. it does not progress in time and stays always at time 0.
After get_next_item there should be a statement like this:
@(posedge dut_ifc1.clk);
What about of monitor ? should there be posedge clk ?
Where else ?
In reply to chr_sue:
In reply to alexd555:
The run_phase of your driver is not a clocked process, i.e. it does not progress in time and stays always at time 0.
After get_next_item there should be a statement like this:
@(posedge dut_ifc1.clk);
Why not clk under block ? begin…end
In reply to alexd555:
What about of monitor ? should there be posedge clk ?
Where else ?
All components connected to the virtual interface has to be synchronized with the clk signal.
In reply to alexd555:
In reply to chr_sue:
Why not clk under block ? begin…end
What about this question ?
Thanks,
Alex
seq_item_port.get_next_item(tx);
@(posedge dut_ifc1.clk)
begin
dut_ifc1.a <= tx.a;
dut_ifc1.b <= tx.b;
dut_ifc1.opcode <= tx.opcode;
end
In reply to alexd555:
This is exactly what I meant.
Note the clock line has to be :
@(posedge dut_ifc1.clk);
Why do you use “;” without “begin…end” ?
In reply to chr_sue:
Hi ,
I am trying to override the class monitor in test:
class test_overide extends uvm_test;
`uvm_component_utils(test_overide)
axi_env m_env;
seq_stimulus m_seq;
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
`uvm_info(“test1 build phase”,“”,UVM_LOW);
set_type_override_by_type(axi_monitor::get_type(),override_monitor::get_type());
m_env = axi_env::type_id::create(“m_env”,this);
endfunction
task run_phase(uvm_phase phase);
phase.raise_objection(this,get_type_name());
`uvm_info(get_type_name,“start test”,UVM_LOW)
m_seq = seq_stimulus::type_id::create(“m_seq”);
if(!m_seq.randomize())
`uvm_error(get_type_name(), “RAndomize failed”)
m_seq.start(m_env.m_axi_agent.m_seqr);
phase.drop_objection(this,get_type_name());
endtask
endclass
getting same error:
Error-[NOA] Null object access
/classes_v/axi_agent.sv, 44
The object at dereference depth 2 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
#0 in \axi_agent::connect_phase at
In reply to ramankaur09:
Is this line 44 of axi_agent?
#0 in \axi_agent::connect_phase at
Please paste the whole line 44.
In reply to chr_sue:
Hello,
ifndef AXI_AGENT_PKG define AXI_AGENT_PKG
import env_pkg::*;
`include “axi_monitor.sv”
class axi_agent extends uvm_agent;
`uvm_component_utils(axi_agent)
axi_sequencer m_seqr ;
axi_driver m_driver;
axi_monitor m_monitor;
//axi_config m_config;
uvm_analysis_port #(stimulus) aport;
uvm_analysis_port #(stimulus) monitor_aport;
virtual axi_intf intf;
function new(string name,uvm_component parent);
super.new(name,parent);
monitor_aport = new(“monitor_aport”, this);
aport = new(“aport”, this);
endfunction
extern virtual function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
endclass: axi_agent
function void axi_agent::build_phase(uvm_phase phase);
if(!uvm_config_db# (virtual axi_intf)::get(this,“”,“intf”,intf))
`uvm_error(“ERROR AGENT”,“BUILD_PHASE”)
m_seqr = axi_sequencer::type_id::create(“m_seqr”,this);
m_driver = axi_driver::type_id::create(“m_driver”,this);
//m_driver.intf = intf;
m_monitor = axi_monitor::type_id::create(“m_monitor”,this);
`uvm_info(“UMONITOR”,get_type_name(),UVM_LOW);
endfunction
function void axi_agent::connect_phase(uvm_phase phase);
m_driver.seq_item_port.connect(m_seqr.seq_item_export);
line 44-> m_monitor.aport.connect(aport);
endfunction
`endif
In reply to ramankaur09:
Two remarks only:
(1)
function new(string name,uvm_component parent);
super.new(name,parent);
monitor_aport = new("monitor_aport", this); // What's this??
aport = new("aport", this);
endfunction
(2) Does your monitor has an analysis port named aport? And did you contruct it?
In reply to chr_sue:
Hi ,
the second line is commented and not used in the code.
monitor has aport and createed via new() in build_phase,
thanks