I posted my toplevel model. You can there is a clock(clk).
calc_driver.sv
include "calc_sequence.sv" class calc_driver extends uvm_driver #(calc_trans);
uvm_component_utils(calc_driver)
virtual calc_if dut_ifc1;
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction: new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(virtual calc_if)::get(this,“”,“dut_vif”, dut_ifc1))
`uvm_fatal(“NOVIF”,{“virtual interface must be set for: “,get_full_name(),”.dut_ifc”});
$display(“driver”);
endfunction: build_phase
task run_phase(uvm_phase phase);
repeat(300)
begin
calc_trans tx;
seq_item_port.get_next_item(tx);
dut_ifc1.a <= tx.a;
dut_ifc1.b <= tx.b;
dut_ifc1.opcode <= tx.opcode;
seq_item_port.item_done();
end
endtask: run_phase
endclass: calc_driver
calc_sequence.sv
class calc_sequence extends uvm_sequence#(calc_trans);
`uvm_object_utils(calc_sequence)
function new(string name = “calc_sequence”);
super.new(name);
endfunction: new
task body();
calc_trans req;
$display("calc_seq");
repeat(300) begin
req = calc_trans::type_id::create("req");
start_item(req);
assert(req.randomize());
finish_item(req);
$display("a = ", req.a);
$display("b = ", req.b);
$display("opcode = ", req.opcode);
end
endtask: body
endclass: calc_sequence
calc_test.sv
class calc_test extends uvm_test;
`uvm_component_utils(calc_test)
calc_env env;
calc_sequence calc_seq;
function new(string name = “calc_test”,uvm_component parent=null);
super.new(name,parent);
endfunction : new
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
env = calc_env::type_id::create(“env”, this);
calc_seq = calc_sequence::type_id::create(“calc_seq”, this);
endfunction : build_phase
task run_phase(uvm_phase phase);
phase.raise_objection(this);
calc_seq.start(env.calc_agent_h.calc_sequencer_h);
phase.drop_objection(this);
endtask : run_phase
endclass : calc_test