Verification Academy
The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it
UVM
UVM-SystemVerilog
,
UVM
alexd555
June 13, 2019, 6:37am
13
What about
Phase ‘uvm.uvm_sched.post_shutdown’ (id=324) No objections raised, skipping phase
?
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