Verification Academy

macros-and-defines

Topic		Replies	Views	Activity
Problem with Macro SystemVerilog SystemVerilog , UVM , constraint-randomization , macros-and-defines		1	925	July 5, 2021
How to use triple tick(```) and backslash (\) in system Verilog macros UVM UVM , Could-you-please-explain-the-concept-for-how-to-use-triple-tick-and-backslash-in-system-verilog-macrosifdef , defines , etc , macros-and-defines		1	923	May 21, 2021