Hi,
I’m seeing an issue with the following macro definition. Please help-
`define random_f16(COMP) \
sign_f16 dist {0:=1, 1:=1}; \
exponent_f16 dist {'hFF :/ 5, 'hFE :/ 5, ['hF8 : 'hFD] :/ 5, ['h08 : 'hF7] :/ 70, ['h02 : 'h07] :/ 5, 'h01 :/ 5, 'h00 :/ 5}; \
fraction_f16 dist { 'h7F :/ 10,\
['h78: 'h7E] :/ 10,\
['h08: 'h77] :/ 60,\
['h01: 'h07] :/ 10,\
'h00 :/ 10 });\
soft f16_``COMP`` == {sign_f16, exponent_f16, fraction_f16};
Usage: random_f16(a0);
Error:
expecting an identifier [SystemVerilog] on the line number where the macro is being used.
sign_f16, exponent_f16, fraction_f16 and f16_* has been defined random bit. Please let me know if you need more info on this.
Thanks