Hi All,
Could you please explain the concept for how to use triple tick(```) and backslash() in system verilog macros(ifdef ,
defines , etc).
Hi All,
Could you please explain the concept for how to use triple tick(```) and backslash() in system verilog macros(ifdef ,
defines , etc).
In reply to amsaveni.c:
There is no such triple tick (```) concept in SystemVerilog.
Backslash \ is used to continue `define text macros that would have normally finished at the end of the current line.