Topics tagged VHDL-SystemVerilog

Topic	Replies	Views	Activity
How to connect interface ports to VHDL module ports SystemVerilog SystemVerilog , systemverilog-interface , VHDL-SystemVerilog	3	1350	April 13, 2020
Uvm_hdl_deposit single bit - mixed verilog/VHDL design - uvm_hdl_check_path support UVM UVM , uvm_hdl_force , uvm_hdl_check_path , uvm_hdl_deposit , VHDL-SystemVerilog	0	1286	January 13, 2020
Connect VHDL natural range to SystemVerilog SystemVerilog SystemVerilog , VHDL-SystemVerilog	1	2127	September 3, 2019

How to connect interface ports to VHDL module ports

SystemVerilog , systemverilog-interface , VHDL-SystemVerilog

3

1350

April 13, 2020

UVM , uvm_hdl_force , uvm_hdl_check_path , uvm_hdl_deposit , VHDL-SystemVerilog

0

1286

January 13, 2020

Connect VHDL natural range to SystemVerilog

SystemVerilog , VHDL-SystemVerilog

1

2127

September 3, 2019