Uvm_hdl_deposit single bit - mixed verilog/VHDL design - uvm_hdl_check_path support

UVM
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Hi,

there’s a design whose top level is system verilog with some nested VHDL unit.

I’m able to deposit values (uvm_hdl_deposit) into VHDL signals if I specify the entire vhdl signal name. I cannot deposit a value into a single bit of the signal.

Is it possible to force or deposit a single bit of a VHDL path?

Furthermore, I tried to use uvm_hdl_check_path. Apparently the command is not recognized.

In general, in case of VHDL, should uvm_hdl_deposit be used in place of umv_hdl_force?

Kind Regards,
Fabio