How to connect interface ports to VHDL module ports

SystemVerilog
, ,
1

Hello,

I have a top module in Systemverilog, containing sub-blocks which are connected with each other by interfaces, one sub-block is in VHDL, and I need to connect it to a Systemverilog sub-block through my interface.

is this possible ? can I access the ports of my interface and connect them one by one to the ports of my VHDL block?

2

In reply to Yasmine4:

Unfortunately there are no standards for interoperability between these standards. You need to read your tool’s User Manual for sharing user-defined types, or contact your tool vendor for support. This mentor sponsored public forum is not for discussing tool specific issues.

3

In reply to dave_59:

I think there has been a mistake, I don’t have tooling issues, I was asking about the feasibilty in terms of systemverilog syntax because I didn’t find examples featuring this.

4

In reply to Yasmine4:

This might answer your quesiton: Instantiating VHDL Design in SV testbench | Verification Academy