In reply to dave_59:
I think there has been a mistake, I don’t have tooling issues, I was asking about the feasibilty in terms of systemverilog syntax because I didn’t find examples featuring this.
In reply to dave_59:
I think there has been a mistake, I don’t have tooling issues, I was asking about the feasibilty in terms of systemverilog syntax because I didn’t find examples featuring this.