Instantiating VHDL Design in SV testbench

SystemVerilog
1

Hi Guys

Can I instantiate a VHDL design in system verilog testbench???

I have verified a VHDL design in SV testbench by building a Verilog wrapper around the design and hence instantiating the later in the SV bench. I want to know if the instantiation is possible without building a wrapper.

2

You can if your simulator has the features to enable it. It should be no different than instantiating a Verilog-2001 module in a SystemVerilog testbench, except that you are allowed more VHDL types as ports than with Verilog.

As with Verilog, there are no interface ports in VHDL. So if you need to connect an interface to a Verilog

interface itf;
  wire A;
  wire B;
endinteface
module DUT(input wire X output wire Y); // this the equivalent entity in VHDL
endmodule
module top;
  itf i1();
  DUT d1(.X(i1.A), .Y(i1.B)); // port connections for Verilog or VHDL
endmodule