system-verilog-module
Topic | Replies | Views | Activity | |
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How to write verilog code to find modulus |
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1 | 7324 | July 24, 2018 |
Why doesn't it update? |
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8 | 2155 | June 26, 2018 |
Calling a test (which is a "module" in a sv file) inside the testbench file (which is a verilog file) |
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2 | 1771 | February 9, 2017 |