system-verilog-module
Topic | Replies | Views | Activity | |
---|---|---|---|---|
How to write verilog code to find modulus | 1 | 6866 | July 24, 2018 | |
Why doesn't it update? | 8 | 1797 | June 26, 2018 | |
Calling a test (which is a "module" in a sv file) inside the testbench file (which is a verilog file) | 2 | 1616 | February 9, 2017 |