Hi,
I wish to know whether we can call a test(which is a “module” in a sv file)for execution inside the testbench file (which is a verilog file) ?
Thanks in advance!
Hi,
I wish to know whether we can call a test(which is a “module” in a sv file)for execution inside the testbench file (which is a verilog file) ?
Thanks in advance!
In reply to Saraswati:
Your question is not very clear. You never call modules for execution; you instantiate modules inside of other modules.
Maybe you are asking if you can instantiate a module compiled in SystemVerilog inside a module restricted to Verilog-only. The answer that is yes; as long as the port data-types of the SystemVerilog module are assignment compatible with Verilog data types.
In reply to dave_59:
Hi Dave,
Thanks for your answer, and by instantiating the module in another module, whatever is inside the module would execute right ?
Thanks!