Calling a test (which is a "module" in a sv file) inside the testbench file (which is a verilog file)

SystemVerilog
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In reply to Saraswati:

Your question is not very clear. You never call modules for execution; you instantiate modules inside of other modules.

Maybe you are asking if you can instantiate a module compiled in SystemVerilog inside a module restricted to Verilog-only. The answer that is yes; as long as the port data-types of the SystemVerilog module are assignment compatible with Verilog data types.