Topics tagged task

Topic	Replies	Views	Activity
Is task or automatic task synthesizable using verilog (not System Verilog)? SystemVerilog SystemVerilog , task	2	401	November 23, 2023
Accesing the elements of a task from outside the task SystemVerilog SystemVerilog , task	1	263	November 8, 2023
How to override or disable uvm_status_e i.e. UVM_HAS_X for specific register or specific task UVM UVM , task , set_report_severity_id_override , GLS-simulation , -UVM-warnings-disable , uvm_status_e	6	584	September 24, 2023
Task function call SystemVerilog SystemVerilog , task	1	497	April 26, 2023
Can we define a task that has no inputs but only outputs? SystemVerilog SystemVerilog , task , no-inputs-to-task	1	778	March 22, 2023
Trying to understand the role of return keyword SystemVerilog SystemVerilog , task , functions	1	560	March 4, 2023
Constraint failure while using a queue in a task UVM UVM , task , sequence-body , queues-systemverilog	2	589	August 30, 2022
Multi thread in DPI-C structure SystemVerilog SystemVerilog , task , dpi-c , multi-thread	2	636	August 30, 2022
Generating random N random events in M clock cycle (N less than M) SystemVerilog SystemVerilog , task , randomization	4	1951	May 23, 2022
Task in systemverilog SystemVerilog SystemVerilog , task , global-variable	3	1162	September 24, 2020
How can a task return a Queue? SystemVerilog SystemVerilog , task , return-data , functions-in-system-verilog	7	7774	July 31, 2020
Distributing task calls between SV implementations in "generate" blocks SystemVerilog SystemVerilog , generate , task , distributor	4	1257	February 27, 2019
Parameterize a function or task SystemVerilog SystemVerilog , parameterized , task	5	15979	September 14, 2018
Code which behaves like each method of a queue SystemVerilog SystemVerilog , task	4	1063	May 31, 2018
Inout default value SystemVerilog SystemVerilog , inout , task , default-value , argument	4	3833	November 22, 2017
Forcing hierarchical nodes through tasks SystemVerilog SystemVerilog , task , hierarchical-reference , task-argument , for	4	3616	October 10, 2017
Can I add Delay in System Verilog function? SystemVerilog SystemVerilog , function , task , fork-join_none-multiple-threads	6	16068	August 21, 2016
Exact difference between $cast as a task and function SystemVerilog SystemVerilog , function , task , cast	4	3892	January 11, 2016
Error in task(run_phase) UVM UVM , task , syntax_error , edaplayground	4	2587	October 5, 2015
Variable clock generation in verilog using task SystemVerilog SystemVerilog , Clock-generator , task , Verilog	0	9502	January 20, 2015
Apply task code to different signals SystemVerilog SystemVerilog , System-Verilog , task	3	2240	October 22, 2014
Can we return data from SystemVerilog task? SystemVerilog SystemVerilog , task , return-data	5	33864	April 18, 2014