Topics tagged task

Topic	Replies	Views	Activity
How can a task return a Queue? SystemVerilog SystemVerilog , task , return-data , functions-in-system-verilog	9	7950	November 26, 2024
Is task or automatic task synthesizable using verilog (not System Verilog)? SystemVerilog SystemVerilog , task	2	428	November 23, 2023
Accesing the elements of a task from outside the task SystemVerilog SystemVerilog , task	1	271	November 8, 2023
How to override or disable uvm_status_e i.e. UVM_HAS_X for specific register or specific task UVM UVM , task , set_report_severity_id_override , GLS-simulation , -UVM-warnings-disable , uvm_status_e	6	624	September 24, 2023
Task function call SystemVerilog SystemVerilog , task	1	520	April 26, 2023
Can we define a task that has no inputs but only outputs? SystemVerilog SystemVerilog , task , no-inputs-to-task	1	850	March 22, 2023
Trying to understand the role of return keyword SystemVerilog SystemVerilog , task , functions	1	608	March 4, 2023
Constraint failure while using a queue in a task UVM UVM , task , sequence-body , queues-systemverilog	2	590	August 30, 2022
Multi thread in DPI-C structure SystemVerilog SystemVerilog , task , dpi-c , multi-thread	2	662	August 30, 2022
Generating random N random events in M clock cycle (N less than M) SystemVerilog SystemVerilog , task , randomization	4	1959	May 23, 2022
Task in systemverilog SystemVerilog SystemVerilog , task , global-variable	3	1183	September 24, 2020
Distributing task calls between SV implementations in "generate" blocks SystemVerilog SystemVerilog , generate , task , distributor	4	1265	February 27, 2019
Parameterize a function or task SystemVerilog SystemVerilog , parameterized , task	5	16268	September 14, 2018
Code which behaves like each method of a queue SystemVerilog SystemVerilog , task	4	1063	May 31, 2018
Inout default value SystemVerilog SystemVerilog , inout , task , default-value , argument	4	3928	November 22, 2017
Forcing hierarchical nodes through tasks SystemVerilog SystemVerilog , task , hierarchical-reference , task-argument , for	4	3706	October 10, 2017
Can I add Delay in System Verilog function? SystemVerilog SystemVerilog , function , task , fork-join_none-multiple-threads	6	16203	August 21, 2016
Exact difference between $cast as a task and function SystemVerilog SystemVerilog , function , task , cast	4	3939	January 11, 2016
Error in task(run_phase) UVM UVM , task , syntax_error , edaplayground	4	2605	October 5, 2015
Variable clock generation in verilog using task SystemVerilog SystemVerilog , Clock-generator , task , Verilog	0	9533	January 20, 2015
Apply task code to different signals SystemVerilog SystemVerilog , System-Verilog , task	3	2263	October 22, 2014
Can we return data from SystemVerilog task? SystemVerilog SystemVerilog , task , return-data	5	34173	April 18, 2014

How can a task return a Queue?

SystemVerilog

9

7950

November 26, 2024

Is task or automatic task synthesizable using verilog (not System Verilog)?

SystemVerilog

SystemVerilog , task

2

428

November 23, 2023

Accesing the elements of a task from outside the task

SystemVerilog

SystemVerilog , task

1

271

November 8, 2023

How to override or disable uvm_status_e i.e. UVM_HAS_X for specific register or specific task

UVM

UVM , task , set_report_severity_id_override , GLS-simulation , -UVM-warnings-disable , uvm_status_e

6

624

September 24, 2023

Task function call

SystemVerilog

SystemVerilog , task

1

520

April 26, 2023

Can we define a task that has no inputs but only outputs?

SystemVerilog

SystemVerilog , task , no-inputs-to-task

1

850

March 22, 2023

Trying to understand the role of return keyword

SystemVerilog

SystemVerilog , task , functions

1

608

March 4, 2023

Constraint failure while using a queue in a task

UVM

UVM , task , sequence-body , queues-systemverilog

2

590

August 30, 2022

Multi thread in DPI-C structure

SystemVerilog

SystemVerilog , task , dpi-c , multi-thread

2

662

August 30, 2022

Generating random N random events in M clock cycle (N less than M)

SystemVerilog

SystemVerilog , task , randomization

4

1959

May 23, 2022

Task in systemverilog

SystemVerilog

SystemVerilog , task , global-variable

3

1183

September 24, 2020

Distributing task calls between SV implementations in "generate" blocks

SystemVerilog

SystemVerilog , generate , task , distributor

4

1265

February 27, 2019

Parameterize a function or task

SystemVerilog

SystemVerilog , parameterized , task

5

16268

September 14, 2018

Code which behaves like each method of a queue

SystemVerilog

SystemVerilog , task

4

1063

May 31, 2018

Inout default value

SystemVerilog

SystemVerilog , inout , task , default-value , argument

4

3928

November 22, 2017

Forcing hierarchical nodes through tasks

SystemVerilog

SystemVerilog , task , hierarchical-reference , task-argument , for

4

3706

October 10, 2017

Can I add Delay in System Verilog function?

SystemVerilog

SystemVerilog , function , task , fork-join_none-multiple-threads

6

16203

August 21, 2016

Exact difference between $cast as a task and function

SystemVerilog

SystemVerilog , function , task , cast

4

3939

January 11, 2016

Error in task(run_phase)

UVM

UVM , task , syntax_error , edaplayground

4

2605

October 5, 2015

Variable clock generation in verilog using task

SystemVerilog

SystemVerilog , Clock-generator , task , Verilog

0

9533

January 20, 2015

Apply task code to different signals

SystemVerilog

SystemVerilog , System-Verilog , task

3

2263

October 22, 2014

Can we return data from SystemVerilog task?

SystemVerilog

SystemVerilog , task , return-data

5

34173

April 18, 2014