Is task or automatic task synthesizable using verilog (not System Verilog)?

SystemVerilog
,
1

Is task or automatic task synthesizable using verilog (not System Verilog)?

2

In reply to Ayesha1:

It should be as long as all the statements inside the task (its body) are synthesizable as well. Understand that the body of code gets expanded into the always block that calls the task.

3

In reply to dave_59:

Thank you Dave!
I am using verilog, not SystemVerilog. This is my code. I am getting error. Do you see any issue here?

module Task (
input [7:0] a,
input [7:0] b,
output reg [7:0] c,
output reg [7:0] d
);
task automatic reverse_bits_task;
input [7:0] in;
output [7:0] out;
integer index;
begin
for (index=0; index<8; index=index+1) begin
out[7-index] = in[index];
end
end
endtask

always @(a,b) begin
    reverse_bits_task(.in(a),.out(c));
    reverse_bits_task(.in(b),.out(d));
end

endmodule