Can we define a task that has no inputs but only outputs?

SystemVerilog
, ,
1

I defined the following task that generates enable, write flag and address. It doesn’t need any inputs. But it produced error upon compilation stating that: No actual value has been specified for a formal argument ‘en’ that does not have a default value. I think it needs to give an initial value for the output but is that logic ? This error should happen to inputs not outputs. Below is my code:

`timescale 1ns/1ps
module tb();

bit clk=0;
always #20 clk =~clk; //40 ns -> 25MHz

task stim_addr_wr_en(output bit en, output bit wr, output bit[5:0] addr);
 @(posedge clk);
 en ='b1;
 wr ='b1;
 addr= 'd12;
 @(posedge clk); 
 addr= 'd14;
 @(posedge clk); 
 wr= 'b0;
 addr= 'd23; 
 @(posedge clk); 
 addr= 'd48;
 @(posedge clk);
 en= 'b0;
 addr= 'd56;  
endtask

initial begin 
 stim_addr_wr_en();
end

initial begin 
 #220;
 $finish();
end
endmodule
2

In reply to Farah_Adel_Fathy:

Your error has nothing to do with inputs versus outputs. When calling a task or function, you must provide the necessary number of arguments (actuals) that have been defined for that task or function (formals). The only way around that rule is providing default formal argument expressions in the declaration. This makes passing actual arguments optional.

bit d_en, d_wr;
bit [5:0] d_addr;
task stim_addr_wr_en(output bit en.       = d_en, 
                     output bit wr        = d_wr, 
                     output bit[5:0] addr = d_addr);

See section 13.5.3 Default argument values in the IEEE 1800-2017 SystemVerilog LRM.