How to override or disable uvm_status_e i.e. UVM_HAS_X for specific register or specific task

I am trying to run GLS simulations where I need to avoid these UVM_HAS_X errors for specific registers in specific task. I also tried using uvm_top.set_report_severity_id_override(UVM_ERROR,“STATUS”,UVM_WARNING) to avoid errors to warning but it converts all errors to warnings. So is there any way that we can control status of specific registers or disabling it in specific task?

In reply to saikittu72:

Where is the error message being reported? Show some code.

In reply to saikittu72:

I belive you are searchin in the wrong place. Physically there is no ‘X’, there is only ‘1’ or ‘0’. If your configuration registers have an undefined value this might cause serious trouble.
You should take care to reset all your registers at the beginning of your simulation.

In reply to chr_sue:

Actually in real time it will be 0 or 1 but in GLS(gate simulations) there will be “X” and I am checking read margin so I sweep delay and it is expected to show x at some point of delay but registers goes to X and recovers after passing that region. During that X region I used to get UVM_HAS_X error which need to be disabled for that register.
How to disable X for that particular region or avoid UVM_ERRORS?

In reply to dave_59:
task run_phase(uvm_phase phase);
start tpgm_generator;
for(i=0;i<=54;i++)begin
set(delay);
clr_registers();
chk_err_cnt(i,err_cnt);
end
end task

task chk_err_cnt(int d,output logic err_cnt);
uvm_status_e status;
uvm_reg_data_t val;
logic err_cnt=0;
case(d) begin
0 : begin
regmap.ECR_DQ_0.mirror();
regmap.ECR_DQ_0.read(.status(status),.value(val));
uvm_info("DEBUG",$sformatf("Complete read DQ0= %0h",val),UVM_NONE) // I cannot read X from regmodel, how to read X? uvm_info(“DEBUG”,$sformatf(“Status DQ0= %s”,status.name),UVM_NONE) // I can see read status as UVM_HAS_X, how to ignore this status?
err_cnt = regmap.ECR_DQ_0.ERR_CNT_DQ_0.get();
$display(“err_cnt check DQ0 = %0h”, err_cnt); // I cannot get X, how to get X?
end

   1 : begin 
        regmap.ECR_DQ_1.mirror(); 
         err_cnt = regmap.ECR_DQ_1.ERR_CNT_DQ_1.get(); 
       end 
 endcase

endtask

In reply to saikittu72:

Then I sak you directly: do you reste your registers at the first step in your simulation?
There might be a weakness in your GLS modeling. Hiding error messages might not be the right way.

In reply to chr_sue:

Yes I agree, hiding is not good solution. But it is expected errors when we sweep delay so we can avoid such violations. Because of these violation I am seeing X in my registers so thinking how to avoid these.
If I do backdoor read i.e. uvm_hdl_read there will be no status errors, thinking how to solve for frontdoor read i.e. regmodel at specific time. can anyone please suggest any good way solution.

Thanks