How to override or disable uvm_status_e i.e. UVM_HAS_X for specific register or specific task

UVM
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5

In reply to dave_59:
task run_phase(uvm_phase phase);
start tpgm_generator;
for(i=0;i<=54;i++)begin
set(delay);
clr_registers();
chk_err_cnt(i,err_cnt);
end
end task

task chk_err_cnt(int d,output logic err_cnt);
uvm_status_e status;
uvm_reg_data_t val;
logic err_cnt=0;
case(d) begin
0 : begin
regmap.ECR_DQ_0.mirror();
regmap.ECR_DQ_0.read(.status(status),.value(val));
uvm_info("DEBUG",$sformatf("Complete read DQ0= %0h",val),UVM_NONE) // I cannot read X from regmodel, how to read X? uvm_info(“DEBUG”,$sformatf(“Status DQ0= %s”,status.name),UVM_NONE) // I can see read status as UVM_HAS_X, how to ignore this status?
err_cnt = regmap.ECR_DQ_0.ERR_CNT_DQ_0.get();
$display(“err_cnt check DQ0 = %0h”, err_cnt); // I cannot get X, how to get X?
end

   1 : begin 
        regmap.ECR_DQ_1.mirror(); 
         err_cnt = regmap.ECR_DQ_1.ERR_CNT_DQ_1.get(); 
       end 
 endcase

endtask