I use following code in my base sequence as I need this to be used in other sequences.
class base_sequence extends uvm_sequence#(sequence_item);
`uvm_object_utils(base_sequence)
//Constructor
function new(string name="base_sequence");
super.new(name);
endfunction : new
sequence_item req;
bit [20:0] me_q[$];
extern virtual task body();
extern virtual task drive_logic(bit[20:0] me_q[$]);
endclass : base_sequence
task base_sequence :: drive_logic(bit[20:0] me_q[$]);
for(int i = 0; i < me_q.size() ; i++) begin
req = sequence_item::type_id::create("simpleme_req");
start_item(req);
assert(req.randomize() with {
req.start_UVM == 1;
req.run_base_UVM == 1;
req.start_count_UVM == 8'd1;
req.clear_status_UVM == 0;
req.final_count_UVM == me_q.size();
{req.base_march, req.base_march_elem} == me_q[i];
req.start_count_UVM < req.final_count_UVM;
});
finish_item(req);
end
endtask
I have used base sequence to develop other sequences. This is the body code for one of the sequence
task selfchk_sequence :: body();
me_q = {21'h100083};
drive_logic(me_q);
endtask : body
But I am having following error message
=======================================================
Solver failed when solving following set of constraints
bit[30:0] me_q.size() = 31’h1;
rand bit[7:0] req.start_count_UVM; // rand_mode = ON
rand bit[7:0] req.final_count_UVM; // rand_mode = ON
constraint WITH_CONSTRAINT // (from this) (constraint_mode = ON) (cbc_sequence_library.svh:60)
{
(req.start_count_UVM == 8’h1);
(req.final_count_UVM == me_q.size());
(req.start_count_UVM < req.final_count_UVM);
}
=======================================================
I came to understand from debug that the solver issue happens when I pass the following line in constraint
req.final_count_UVM == me_q.size();
The error is gone when I gave a sample run commenting it out. How to solve this situation while using a task inside body() method