Generating random N random events in M clock cycle (N less than M)

SystemVerilog
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Hi,

I am new to SystemVerilog. I am writing a simple task which can create N events in M cycles randomly(N is less than M). An event is said to be created when a signal (let’s say force_event) is high for one cycle.

Can someone help with this? Thanks.

2

In reply to stupidkris1010:
You left a lot of details out, but if this task is taking M as an argument and returns after M cycles, you could create an array of bits and set them to create an event

task randevents(int M)
  bit list[];
  list = new[M]; // creates a list of M bits
  randomize (list) with {list.sum(int'(item)) < M}; // constrain the sum of bit to be less than M
  foreach(list[ii]) @(posedge clock) force_event <= list[ii];
endtask
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In reply to dave_59:

Hi Dave,

Sorry for late reply and leaving a lot of details undeclared. But your solution helped me solve my problem.

Thanks.

4

In reply to dave_59:

In reply to stupidkris1010:
You left a lot of details out, but if this task is taking M as an argument and returns after M cycles, you could create an array of bits and set them to create an event

task randevents(int M)
bit list[];
list = new[M]; // creates a list of M bits
randomize (list) with {list.sum(int'(item)) < M}; // constrain the sum of bit to be less than M
foreach(list[ii]) @(posedge clock) force_event <= list[ii];
endtask

i want full code

5

In reply to mahendray:

So did I, but we never got it.