Generating random N random events in M clock cycle (N less than M)

SystemVerilog
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4

In reply to dave_59:

In reply to stupidkris1010:
You left a lot of details out, but if this task is taking M as an argument and returns after M cycles, you could create an array of bits and set them to create an event

task randevents(int M)
bit list[];
list = new[M]; // creates a list of M bits
randomize (list) with {list.sum(int'(item)) < M}; // constrain the sum of bit to be less than M
foreach(list[ii]) @(posedge clock) force_event <= list[ii];
endtask

i want full code