Task function call

SystemVerilog
,
1

Hi Sir
This is my task in my case:

task automatic get_user_cmd_list_value(string cmd_name, output logic [15:0] cmd_value,output logic [15:0] cmd_address);
    for (int i = 0; i < user_cmd_list.size(); i++) 
        begin
            if (user_cmd_list[i].name == cmd_name) 
                 begin
                      cmd_value   = user_cmd_list[i].command;
                      cmd_address = user_cmd_list[i].address;
                      $display("Command for name %s; command is %h; address is ", cmd_name, cmd_value,cmd_address);
                      return;
                 end
            end
    $error("Command not found for name %s", cmd_name);
endtask

But when i want to invoke its at other sv file,i met an error:
if i

       logic [15:0] cmd;
       logic [15:0] reg_addr;
       get_user_cmd_list_value("TEST1",cmd);

Result is correct,i can get cmd value.but if i use this sentence,Xcelium report an error:

get_user_cmd_list_value("TEST1",,reg_addr);

Explicit default argument not declared for corresponding formal argument [SystemVerilog]

I’m curious about this issue. If the parameter cannot be omitted, why is the first case correct? Can you help me with this?

2

In reply to ncui:

See Can we define a task that has no inputs but only outputs ? | Verification Academy