Topic	Replies	Views	Activity
UVM print topology in end of elaboration and start of simulation UVM UVM , Cookbook-UVM	2	512	December 6, 2022
Register model for a register that can be either RO or WO based on another register setting UVM UVM , Cookbook-UVM	2	442	June 16, 2022
Set/get of queue from test to scoreboard UVM UVM , Cookbook-UVM , Queue-get-and-set , uvm_config_db-of-queue-get-and-set	1	835	October 29, 2021
How a test case will execute after calling global task run_test(); UVM UVM , Cookbook-UVM	1	651	June 22, 2021
Porting UVM Env between different customer projects UVM UVM , Cookbook-UVM	4	971	July 2, 2020
How many ways to start sequence? UVM UVM , Cookbook-UVM	7	3498	October 30, 2017
Difference between uvm_sequence_item and uvm_transcation? UVM UVM , Cookbook-UVM	4	10137	August 16, 2017
Hi ..! UVM UVM , Cookbook-UVM	1	1319	May 16, 2016
Why build phase is top-down and rest of all are in bottom up? UVM UVM , Cookbook-UVM	1	5607	October 18, 2015
What's raise and drop objection? UVM UVM , Cookbook-UVM	1	1835	October 16, 2015
What's advantage of using TLM port ? In sv we were using Mailbox and in UVM we are using TLM port then what's advantage? UVM UVM , Cookbook-UVM	2	5400	October 16, 2015
Why better to put sequencer , driver, monitor in agent and then put in environment? UVM UVM , Cookbook-UVM	1	1507	October 16, 2015
What is difference between UVM_CONFIG_DB and (set_config_object or set_config_int or set_conifg_str)? UVM UVM , Cookbook-UVM	1	2573	October 16, 2015
Go go back to completed phase of run phase UVM UVM , Cookbook-UVM	0	1255	October 16, 2015

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