Topic	Replies	Views	Activity
Question on testcase and checkers UVM UVM , Checkers , testcase	2	823	November 23, 2021
Can we extend seq_item or sequence in test class? UVM UVM , sequence , testcase , sequence_item	3	882	September 29, 2020
Stop Sequence UVM UVM , sequence , raise-objection , testcase	2	1062	August 6, 2020
Test cases,Regression & Debugging of any Soc Design SystemVerilog SystemVerilog , Debug , testcase , regression , Test-cases , Regression--Debugging-Soc-Design	4	3700	July 1, 2020
How to stop or kill the running sequences UVM UVM , end-of-test-mechanism-in-UVM , sequence-and-sequencer , testcase	15	25818	December 3, 2017
How to choose a testcase class from command line on SV SystemVerilog SystemVerilog , Polymorphism , Command-Line-Processing , valueplusargs , testcase	2	4290	June 2, 2016

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