Hi,
I am having testcase classes as one base and 2 derived classes. How can i choose a particular test from command line in native SystemVerilog. i.e. I am trying to achieve it by Polymorphism. But I do not know how to change the string type of command line extractor value($value$plusargs) to class type to achieve polymorphism. I know it is easy to do that in UVM with +UVM_TESTNAME=test1 / +UVM_TESTNAME=test2 / +UVM_TESTNAME=test_base. Please suggest me here.
code snippet:
class test_base;
virtual task run();
int addr;
int data;
$display("I am from Test Base class");
addr = 10;
data = 10;
endtask
endclass
class test1 extends test_base;
task run();
int addr;
int data;
$display("I am from Test1 derived class");
addr = 20;
data = 20;
endtask
endclass
class test2 extends test_base;
task run();
int addr;
int data;
$display("I am from Test2 derived class");
addr = 30;
data = 30;
endtask
endclass
module top;
string test_name;
test_base test;
//typedef class T;
initial begin
test = new();
if($value$plusargs("TEST_CASE=%s",test_name)) begin // I am passing TEST_CASE=test1
test_name t1; // how to change the string type to class type??
test = t1;
test.run(); // trying to run derived class test by override the virtual method run
$display("test_name = %s", test_name);
end
else begin
test.run(); // running base class test
end
$finish;
end
endmodule