Where is the best place to put the register model?
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0
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275
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December 21, 2023
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Is it possible to map 2 different sequencers to a reg_map one for read one for write?
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18
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1354
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December 16, 2022
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Set sub register block from the top register block to below component hierarchy
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2
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633
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March 10, 2022
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Reuse constraints in child classes
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1
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1048
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February 15, 2021
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UVM_BIG_ENDIAN - Address order when n_bytes is set to 1
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0
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1258
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November 20, 2019
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UVM 1.2 new warning - a resource with meta characters in the field name has been created
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11
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7105
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April 9, 2019
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RAL: uvm_reg_map base address does not work
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3
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2730
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March 5, 2018
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How the SPI reg2bus/bus2reg functionality taken care in "a complete working example uvm_spi_bl_reg_tb.tgz"?
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3
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1071
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December 9, 2017
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Register model integration, set_inst_override_by_type
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4
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2158
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May 19, 2015
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Shared address maps in uvm_reg_block
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1
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3278
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December 24, 2014
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Special register(s) with fields based on a mode
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0
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1896
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April 16, 2014
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Cannot predict while reg is being accessed
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0
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1313
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April 7, 2014
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Register callback to uvm_reg_block model
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0
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2191
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March 13, 2014
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