Set sub register block from the top register block to below component hierarchy

UVM
, ,
1

Hi Team,

I have these kind of uvm_reg_block.

class system_reg_block extends uvm_reg_block;
    subsytem_reg_block_1 ss_rb_1;
    subsytem_reg_block_2 ss_rb_2;
    ...
    ...

endclass

class top_reg_block extends uvm_reg_block;
     system_reg_block s_rb;
    
    ...
    ...

endclass

my intention is to set(uvm_config_db) subsystem_reg_block_1 from class top_reg_block via reg_block instance system_reg_block(without instantiating subsystem_reg_block_1 in top_reg_block class).

Is it possible to achieve??
if yes, kindly show me the way…

Thanks,
jj_bukhari

2

In reply to jj_bukhari:

This is an XY problem. Please explain what led you to come up with this request.

3

In reply to dave_59:

Hi dave,

Thanks for the reply.

Actually, I am working on SOC level Testbench. which consist of separate sub-system within it
and respective RAL model. also I have SOC level RAL model which consist all present sub-system RAL model in it.

I have a TestBench structure where I can verify the separate sub-system RAL model individualy. and SOC level RAL model as well.

Now, I want to verify perticular sub-system RAL model via SOC RAL model(to check if it takes lesser run time than the individual sub-system).

I hope, I could make it clear.

Thank you.