UVM_BIG_ENDIAN - Address order when n_bytes is set to 1

UVM
, , ,
1

Good day!

SCENARIO1: (I’m just pasting portions of codes just to explain my settings)

  • I have a uvm_reg_block class, where I created a map like below (n_byte is set to 1):
    reg_block_map_byte = create_map(“reg_block_map_byte”, 32’h00000000, 1, UVM_BIG_ENDIAN, 1);
  • I add a register as below :
    reg_block_map_byte.add_reg(REG00, 'h0000, “RW”);
  • This register configured registerfield as below:
    FIELD0.configure (this, 8, 24, “RW”, 0, 8’h00, 1, 1, 1);
    FIELD1.configure (this, 8, 16, “RW”, 0, 8’h00, 1, 1, 1);
    FIELD2.configure (this, 8, 8, “RW”, 0, 8’h00, 1, 1, 1);
    FIELD3.configure (this, 8, 0, “RW”, 0, 8’h00, 1, 1, 1);
  • On my sequence I write to this register :
    REG_BLOCK.REG00.write( status, 32’hAABBCCDD)

SCENARIO2: (All are same except that I change the endianness to UVM_LITTLE_ENDIAN)

RESULTS :
(SCENARIO1/BIG ENDIAN) : Produces actual stimulus that sends 4 Register Write Byte Access with addresses 0x03, 0x02, 0x01 and 0x01 respectively
(SCENARIO2/BIG ENDIAN) : Produces actual stimulus that sends 4 Register Write Byte Access with addresses 0x00, 0x01, 0x02 and 0x03 respectively

QUESTION :
Is there a way that even though I use UVM_BIG_ENDIAN, the address generated will still be 0x00, 0x01, 0x02 and 0x03 respectively?
Note : My register block/module in the DUT is BIG Endian (byte 0 = data[31:24]), In this particular register REG00, I am waiting until complete
new data is written (32bits),i.e. when 0x03 address is written. But since it is the first address generated by the uvn ral access, the DUT
will start its processing using REG00 with value 32’h000000DD.

Thanks to all who can give their inputs!

Regards,
Fed