Verification Academy

clocks-do-not-agree-in-cycle-delay-sequence-operator

Topic		Replies	Views	Activity
It seems there is something wrong with'##2 rtr_io.cb.reset_n <= 1'b1' in Test Program since compiling tool sends error that 'a default clocking block must be specified to use the ##n timing statement'. Can someone help to correct the test program? Thx! SystemVerilog SystemVerilog , Clocking-Block , clocks-do-not-agree-in-cycle-delay-sequence-operator		4	892	May 13, 2022
Leading clock mismatch error in a multi-clock property SystemVerilog SystemVerilog , Multi-clock-sequence , multi-clock-property , clocks-do-not-agree-in-cycle-delay-sequence-operator		3	1681	March 6, 2018