Verification Academy

conditional-compilation

Topic		Replies	Views	Activity
Conditional instantiation of components UVM UVM , activepassive-agent-configuration , uvm-config_db , conditional-compilation		0	411	July 5, 2022
Generate generic signals for different dut in the same test SystemVerilog SystemVerilog , conditional-compilation , Post-synthesis-model , Post-place-and-route-model , Generic-conection		2	749	March 9, 2021