Generate generic signals for different dut in the same test

SystemVerilog
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1

I am validating a design in vhdl with systemverilog (not UVM) Currently I have a wrapper for the DUT and a test connected with interfaces, right now I need to validate the post synthesis simulation model and the post place and route simulation model of the same design.

I use conditional compilation to compile the test depending on the used DUT. The code of the test is the following:


 begin : resource_1
  `ifdef functional
     @(posedge dut.window.theVI.ViControlx.tDiagramEnableIn); //Wait for a dut signal
  `elsif synthesis
     @(posedge dut.window_theVI_ViControlx_EnableInBlk_tEnableInLoc_18346);  //Wait for a dut signal
  `elsif par
  `endif 
   resource1.execute();
 end  : resource_1

I want to avoid using conditional compilation in the test, making these signals as generic and assigning them in an external file (with conditional compilation). Is this possible? Thanks

2

In reply to igsiguero:

It is not clear why you want to do this, but you can certainly use a macro that is defined in an external file that has the conditional compilation in it.

external file:

`ifdef functional
  `define d_wait @(posedge dut.window.theVI.ViControlx.tDiagramEnableIn); //Wait for a dut signal
`elsif synthesis
  `define d_wait @(posedge dut.window_theVI_ViControlx_EnableInBlk_tEnableInLoc_18346);  //Wait for a dut signal
`elsif par
  `define d_wait
`endif

test code:

begin : resource_1
   `d_wait
   resource1.execute();
end  : resource_1
3

In reply to dave_59:

Thank you Dave, worked fine for me. I wanted it to make the test code more readable.