Generate generic signals for different dut in the same test

SystemVerilog
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2

In reply to igsiguero:

It is not clear why you want to do this, but you can certainly use a macro that is defined in an external file that has the conditional compilation in it.

external file:

`ifdef functional
  `define d_wait @(posedge dut.window.theVI.ViControlx.tDiagramEnableIn); //Wait for a dut signal
`elsif synthesis
  `define d_wait @(posedge dut.window_theVI_ViControlx_EnableInBlk_tEnableInLoc_18346);  //Wait for a dut signal
`elsif par
  `define d_wait
`endif

test code:

begin : resource_1
   `d_wait
   resource1.execute();
end  : resource_1