Registration and check-in

Coffee and networking with your peers.

Welcome/Intro

Todd Holbrook | Sr. AE Manager

AI-Driven Functional Verification: Embedded Intelligence and Agentic Workflows

Sunil Sahoo | Product Manager - Simulation

This session demonstrates how embedded AI with agentic workflows accelerates functional verification across simulation, static analysis, and formal verification. It explores generating assertions and RTL from specifications, guiding stimulus toward uncovered scenarios, prioritizing regressions through failure prediction, and accelerating debug through failure-signature clustering and root-cause analysis. The session examines how RAG, knowledge graphs, and MCP interfaces connect goal-driven agents to design context and verification engines. Attendees will gain a technical perspective on integrating AI into verification workflows, with clear distinctions between production capabilities, emerging features, and the roadmap toward autonomous orchestration.

Improving Testplan-Driven Verification with Agentic Workflows

Austin Mam | VIQ Product Specialist

Leverage agentic workflows to jumpstart your testplan creation by generating testplans from existing specifications. Learn more about how AI can assist your testplan-driven flows with creation, modification, and tracking.

Complimentary Lunch and networking

Questa One Debug Agent: Accelerating Simulation Failure Analysis from Detection to Root Cause

Athira Panicker | Product Engineer

As designs and testbenches grow more complex, identifying the cause of a simulation failure can become a time-consuming bottleneck. This presentation explores the QuestaOne Debug Agent, which guides engineers through a structured workflow from failure characterization and triage to root-cause analysis. The agent traces testbench driver activity into the design and uses waveform debugging to examine signal behavior and timing around the failure. By recording evidence and recommending targeted fixes and validation steps, it helps make debug investigations more focused and actionable.

Questa One Software-Aware Verification IP: Simplifying HW/SW Co-Simulation for Faster, Earlier, and More Reliable SoC Validation

Bob Oden | Application Engineer

Modern SoC design cycles are accelerating. At the same time, hardware increasingly relies on software to define key product features. Because of these concurrent shifts, early software bring-up and system-level validation have become critical bottlenecks in the overall verification flow. This presentation explores Avery Software-Aware VIP (SAV), a verification approach that integrates QEMU, Fast Processor Models, and virtualized SoC environments to deliver realistic software driven stimulus within your UVM or SystemVerilog testbench.

TopGolf happy hour & networking