Compute Subsystem RTL Signoff with CSS VIP and Software Aware VIP

This session highlights a robust methodology to accelerate the development and verification of Compute Subsystems such as Arm® Neoverse™ V3 based and also RISC-V based Compute Subsystem (CSS)-based designs, with a shift-left in simulation and signoff using Avery Protocol VIP, CSS VIP, Software Aware VIP, Arm Fast Models and QEMU models.

Guest Presenter: Purna Mohanty – Signature IP

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