Accelerating Innovation: PCIe Gen7 Verification for High-Speed Design
This session will delve into the advanced features of Avery’s PCIe Verification IP, including dynamic testbench creation, sophisticated traffic generation, error injection, and protocol compliance checks. Discover how this native SystemVerilog/UVM VIP enables rigorous testing of performance, power efficiency, and scalability, ensuring designs meet demands of next-generation PCIe applications. Guest Speaker: Ganesh Venkatakrishnan from Scaleflux presented his experience with the Avery PCIe VIP.
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