FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Verification Horizons Blog

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Fremont, CA

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

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Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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SIEMENS Verification Academy

Revolutionizing RTL Design: Unveiling the Latest Updates and Roadmap of the Questa Simulation Platform

During this session we will unveil our latest Questa Simulation platform updates, with a behind-the-scenes look at our strategic investments in expanding functionality, enhancing performance, and delivering more intuitive debug capabilities.

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Full-access members only

Register your account to view Revolutionizing RTL Design: Unveiling the Latest Updates and Roadmap of the Questa Simulation Platform

Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.

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