Verifying Chiplet Interconnects at Scale: UCIe® 3.0

This session highlights what’s new in UCIe 3.0 and explains how Avery UCIe Verification IP enables faster bring-up, deeper protocol coverage, and reduced risk by validating compliance, corner cases, and system-level behavior—helping teams confidently deliver robust chiplet-based silicon.

Guest Presenter: Jie Ding – Ayar Labs

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