Debugging RTL and UVM in Post-sim and Live-sim in the Visualizer Debug Environment
The Visualizer Debug Environment is the debug framework for simulation, static, formal, emulation, prototyping, analog and more. Visualizer and the Questa QIS technology ensures the fastest simulation while logging and prevents mismatches between regression simulations and debug simulations. Visualizer raises the debug abstraction using the Transaction viewer, the FSM view, the logic cone and the schematic viewer. Complex UVM testbench can be debugged easily in the wave window.
Full-access members only
Register your account to view Debugging RTL and UVM in Post-sim and Live-sim in the Visualizer Debug Environment
Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.