New Master’s-level Course

Functional Verification of Digital Logic

Login and View!

Debug Webinar

Wednesday, Mar 05th-8:00 AM PST

Faster Debug of Complex Testbenches Using Visualizer

Register Now!

ISO 26262 Webinar

Wednesday, Mar 12th-8:00 AM PDT

Safety Analysis for Automotive Chips Based on ISO 26262

Register Now!

IC/ASIC & FPGA Trends

2024 Siemens EDA and Wilson Research Group Functional Verification Study

Now Available!

Safety & Security Webinar

FPGA Equivalence Checking from RTL to the Bitstream

On-Demand
SIEMENS Verification Academy

Mastering UCIe 2.0 Verification: Ensuring Seamless Chiplet Integration

This session will focus on the Siemens Avery UCIe Verification IP and the new UCIe2.0 features. Discover its capabilities in dynamic environment creation, including generating complex SiP topologies, portable traffic generation, error injection, and debugging all within a native SystemVerilog/UVM framework.

This content is reserved for members. Register new account or login to view.

Full-access members only

Register your account to view Mastering UCIe 2.0 Verification: Ensuring Seamless Chiplet Integration

Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.

Register account