VHDL 2008: Why It Matters
VHDL 2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed- and floating-point math packages. VHDL 2008 is the largest change to VHDL since 1993; this track is designed to explain the value of the new VHDL 2008 improvements for both Design and Verification Engineers. It is time to start using the new language features to simplify your RTL coding and facilitate the creation of advanced verification environments.
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Sessions
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VHDL-2008 Overview
This session is a brief overview of all the VHDL 2008 improvements. -
Testbench Enhancements
Through extended and new capability, VHDL 2008 enables the creation of advanced verification environments. This session examines these changes and the value they deliver. -
RTL Enhancements
VHDL 2008 enhancements simplify RTL coding. Among these changes are simplified sensitivity lists, simplified conditionals (if statements), and simplified case statements. This session examines these changes and the value they deliver. -
Operator Enhancements
This session will discuss the value of the many new enhancements to the VHDL 2008 operators including Unary reduction, Array operations and mods for physical time. -
Package Type Enhancements
VHDL 2008 includes numerous tune ups to the packages and how the packages are integrated into the language. The session explores the new packages and modifications to the packages as well as the value these updates deliver. -
Fixed Point Package
The new package, fixed_generic_pkg, defines fixed point math types and operations. This session will explain the details of the new package. -
Floating Point Package
The new package, float_generic_pkg, defines floating point math types and operations. This session will explain the details of the new package.
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Forum Discussion - VHDL
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QCX not activating with optimized UVM testbench (qsim only, no qopt -qcx license)
Jun 17, 2026 Coverage -
[SVA Question] Signal 'b' has to toggle only once within 10cycle window of signal 'a' after 'a' is asserted
May 05, 2026 SystemVerilog -
Why is `OUT_MEM_BANK[3] = 101` instead of expected 0x03 in my Verilog bit rearrangement task?
Jul 07, 2025 SystemVerilog
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Session Overview
VHDL 2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed- and floating-point math packages. VHDL 2008 is the largest change to VHDL since 1993; this track is designed to explain the value of the new VHDL 2008 improvements for both Design and Verification Engineers. It is time to start using the new language features to simplify your RTL coding and facilitate the creation of advanced verification environments.