Constraint to generate pattern

SystemVerilog
1

Hi,

I am new to constraints and trying my way around it.

I want to generate a pattern where there should be total 8 1’s and all the 1’s should be in pair and 2 pair should not be next to each other. for eg. a=32’b11001100001100000000000001100000.

please find EDA link below where I don’t get desired results.

EDA link

Thanks,
YC

2

Hi @Yogesh_c,
You can try to randomize an array with random values as index for your addr variable and use post_randomize() function to fill addr variable to easily solve the problem.
Here is the modified class example:
EDA Code
Hope this can help you.

Thanks,
Darshil

1 Like
3

I think of it as “8 bits set, 2 in a row but not 3 in a row”. The edge cases (index 0, 31) are annoying, it would be nice to have a general solution, didn’t find it.

3 Likes
4

Thanks @aaronferrucci its very helpful and interesting solution!! i didn’t think of it.

5

Thanks @Darshil_007 for the solution!!